1. Field of the Invention
This invention relates to the manufacture of an integrated circuit and more particularly to the formation of an n-channel and/or p-channel transistor having barrier atoms incorporated in a lateral area under the drain-side of a gate dielectric to enhance transistor performance.
2. Description of the Related Art
Fabrication of a MOSFET device is well known. Generally speaking, MOSFETs are manufactured by placing an undoped polycrystalline ("polysilicon") material over a relatively thin gate oxide. The polysilicon material and gate oxide are then patterned to form a gate conductor with source/drain regions adjacent to and on opposite sides of the gate conductor. The gate conductor and source/drain regions are then implanted with an impurity dopant material. If the impurity dopant material used for forming the source/drain regions is n-type, then the resulting MOSFET is an NMOSFET ("n-channel") transistor device. Conversely, if the source/drain dopant material is p-type, then the resulting MOSFET is a PMOSFET ("p-channel") transistor device.
Integrated circuits utilize either n-channel devices exclusively, p-channel devices exclusively, or a combination of both on a single substrate. While both types of devices can be formed, the devices are distinguishable based on the dopant species used. The methods by which n-channel devices and p-channel devices are formed entail unique problems associated with each device. As layout densities increase, the problems are exacerbated. N-channel devices are particularly sensitive to so-called short-channel effects ("SCE"). The distance between a source-side junction and a drain-side junction is often referred to as the physical channel length. However, after implantation and subsequent diffusion of the junctions, the actual distance between junctions becomes less than the physical channel length and is often referred to as the effective channel length ("Leff"). In VLSI designs, as the physical channel becomes small, so too must the Leff. SCE becomes a predominant problem whenever Leff drops below approximately 1.0 .mu.m.
A problem related to SCE and the subthreshold currents associated therewith, but altogether different, is the problem of hot-carrier effects ("HCE"). HCE is a phenomena by which the kinetic energy of the carriers (holes or electrons) is increased as they are accelerated through large potential gradients and subsequently become trapped within the gate oxide. The greatest potential gradient, often referred to as the maximum electric field ("Em") occurs near the drain during saturated operation. More specifically, the electric field is predominant at the lateral junction of the drain adjacent the channel. The electric field at the drain primarily causes electrons in the channel to gain kinetic energy and become "hot".
As hot electrons travel to the drain, they lose their energy by a process called impact ionization. Impact ionization serves to generate electron-hole pairs, wherein the pairs migrate to and become injected within the gate dielectric near the drain junction. Traps within the gate dielectric generally become electron traps, even if they are partially filled with holes. As a result, there is a net negative charge density in the gate dielectric. The trapped charge accumulates with time, resulting in a positive threshold shift in the NMOS transistor, or a negative threshold shift in a PMOS transistor. It is known that since hot electrons are more mobile than hot holes, HCE causes a greater threshold skew in NMOS transistors than PMOS transistors. Nonetheless, a PMOS transistor will undergo negative threshold skew if its Leff is less than, e.g., 0.8 .mu.m.
It is therefore desirable to develop a technique for fabricating transistors with reduced hot carrier injection into and trapping within the drain-side of a gate dielectric. Such a fabrication technique is necessary to prevent the accumulation of trapped charge within a gate dielectric, which would further help prevent the threshold voltage of a transistor from varying from its design specification. Since several types of semiconductor devices rely on the stability of transistor threshold voltage, uniformity of threshold voltage is desirable. The presence of a highly uniform and stable threshold voltage would provide for a highly reliable integrated circuit.